Package substrate

ABSTRACT

According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 μm in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 μm in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern  58 M is formed between conductor circuits  58 U and  58 U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

This is a Divisional of National Application Ser. No. 09/529,597 filedMay 31, 2000, which is the National Phase under 35 U.S.C. §371 ofInternational Application No. PCT/JP98/04350, filed Sep. 28, 1998.

BACKGROUND ART

The present invention relates to a package board on which an IC chip isto be mounted, more particularly, a package board provided withsoldering pads on its top and bottom surfaces. The soldering pads areconnected to the IC chip, as well as to boards such as a mother board, asub-board, etc.

A highly integrated IC chip is mounted on the package board andconnected to a mother board, a sub-board, etc. Hereunder, aconfiguration of this package board will be described with reference toFIG. 23, which is a cross sectional view of the package board 600provided with an IC chip 80 and mounted on a mother board 90. Thepackage board 600 includes conductor circuits 658A and 658B formed onboth surfaces of its core board 630. Furthermore, conductor circuits658C and 658D are formed in the upper layer of the conductor circuits658A and 658B with an interlaminar resin insulating layer 650therebetween respectively. On the upper layer of the conductor circuits658C and 658D is formed an interlaminar resin insulator 750. In theinterlaminar resin insulating layer 650 are formed via-holes 660A and660B and in the interlaminar resin insulator 750 are formed via-holes660D and 660C respectively. On the other hand, on the top surface of thepackage board on which the IC chip 80 is mounted are formed solderingbumps 676U connected to the pads 82 formed on the IC chip 80 sidesurface of the package board. On the bottom surface of the package board600 on which a sub-board 90 is mounted are formed soldering bumps 676Dconnected to the pads 92 formed on the mother board 90 side surface ofthe package board 600. Each of the soldering bumps 676U is formed on asoldering pad 675U. Each of the soldering bumps 676D is formed on asoldering pad 675D. In order to more improve the connection reliabilityof the soldering bumps 676U and 676D, resin 84 is sealed in a clearancebetween the IC chip 80 and the package board 600. In the same way, resin94 is sealed in a clearance between the package board 600 and the motherboard 90.

As described above, the package board 600 is used to connect the highlyintegrated IC chip 80 to the mother board 90. The pads 82 formed on theIC chip 80 side surface are as small as 133 to 170 μm in diameter andthe pads 92 formed on the mother board 90 side surface are as large as600 μm in diameter. Consequently, the IC chip 80 cannot be attacheddirectly to the mother board 90. This is why the package board 600 isdisposed between the IC chip 80 and the mother board 90.

The package board 600 is formed so as to match both IC chip sidesoldering pads 675U and mother board side soldering pads 675D with bothIC chip side pads 82 and bother board side pads 92 in size respectively.Consequently, the rate of the area occupied by the soldering pads 675Uon the IC chip side surface of the package board 600 differs from therate of the area occupied by the soldering pads 675D on the mother boardside surface of the package board 600. And, both interlaminar resininsulator 650 and core board 630 are made of resin and the solderingpads 675U and 675D are made of a metallic material such as nickel.Consequently, when the resin portions of the interlaminar resininsulating layers 650 and 750 are shrunk due to curing, drying, etc. inthe manufacturing process, the package board is warped toward the ICchip side sometimes. This is because of a difference in the rate of thearea occupied by the soldering pads between 675U on the IC chip sidesurface and 675D on the mother board side surface of the package board600 as described above. In addition, when in an actual usage of thepackage board 600 on which an IC chip is mounted, the heat generatedfrom the IC chip makes the package board expand and shrink repetitively,causing a difference of shrinkage factor between the resin portion andthe metallic portion of those soldering pads. And, this results inwarping of the package board 600 sometimes.

In the case of a multi-layer board used as such a package board, one ofa plurality of conductor circuit layers is generally used as a groundlayer or a power supply layer to reduce noise or for other purposes. Inthe case of a multi-layer wiring board manufactured by a conventionaltechnology as shown in FIG. 23, however, the ground layer (or the powersupply layer) is connected to an external terminal via a wire. In otherwords, wires 658A and 658B (conductor circuits) used as ground layersare formed on the upper layer of the board 630. The wiring (groundlayer) 658B is connected to the wiring 658D-S through a via-hole 660Band the wiring 658D-S is connected to the soldering bump 676U through avia-hole 660D.

Since the ground layer 658D is connected to the soldering bump 676U viathe wiring 658D-S in this case, the wiring 658D-S is apt to generatenoise and the noise causes malfunctions in electric elements such as anIC chip connected to the multi-layer wiring board. In addition, such themulti-layer wiring board needs a space for wiring in itself and thismakes it difficult to realize higher integrated printed wiring boards.

On the other hand, a package board generally includes capacitors thereinused to reduce noise from signals transmitted between the IC chip andthe mother board. In an embodiment as shown in FIG. 23, inner layerconductor circuits 658A and 658B provided on both surfaces of the coreboard 630 are used as a power supply layer and a ground layer, so thatcapacitors are formed between the core board 630 and the power supplylayer and the ground layer respectively.

FIG. 24A is a top view of the inner conductor circuit layer 658B formedon the top surface of the core board 630. On the inner conductor circuitlayer 658B are formed a ground layer 638G, as well as land-pads 640 forconnecting the top layer to the bottom layer. And, around each of theland-pads 640 is formed an insulating buffer 642.

Each of the land-pads 640 consists of a land 640A of a through-hole 636of the core board 630 shown in FIG. 23, a pad 640b connected to avia-hole 660A going through the upper interlaminar resin insulatinglayer 650, and a wire 640c connecting the land 640a to the pad 640b.

In the case of a package board manufactured by the conventionaltechnology, the land 640a is connected to the pad 640b via the wiring640c. Consequently, the transmission path provided between the upperconductor layer and the lower conductor layer is longer, so that thepackage board has confronted with problems that the signal transmissionslows down and the connecting resistance increases.

Furthermore, as shown in FIG. 24A, a corner K is formed at a jointbetween the wiring 640c and the land 640a, as well as at a joint betweenthe wiring 640c and the pad 640b respectively. And, stress isconcentrated on each of those corners K due to a difference of thermalexpansivity between the core board 630/interlaminar resin insulatinglayer 650 made of resin and the land pad 640 made of a metallic material(copper, etc.). This causes a crack L1 to be generated sometimes in theinterlaminar resin insulating layer 650 as shown in FIG. 23, resultingin breaking of a wire in the conductor circuit 658D or the via-hole 660Dformed in the interlaminar resin insulating layer 650.

On the other hand, the mother board 90 side soldering bumps 676D areconnected to the inner conductor circuit layer 658C through thevia-holes 660D, the wiring 678, and the soldering pads 675. FIG. 24Bshows an expanded view (C direction) of both via-hole 660D and solderingbump 675D shown in FIG. 23. A soldering bump 675 on which a solderingbump 676D is mounted is formed circularly and connected to acircularly-formed via-hole 660D through the wiring 678.

The IC chip 80 repeats the heat cycle between high temperature during anoperation and cooling down up to the room temperature at the end of anoperation. Since the thermal expansivity differs significantly betweenthe IC chip 80 made of silicon and the package board 600 made of resin,stress is generated in the package board in the heat cycle, causing acrack L2 to be generated in the sealing resin 94 provided between thepackage board 600 and the mother board 90. And, such a crack L2 isextended thereby to disconnect the via-hole 660D from the soldering bump675D of the package board 600 sometimes. In other words, as shown inFIG. 24C for an expanded view (D direction) of the via-hole 660D and thesoldering bump 675 shown in FIG. 23, sometimes a crack L2 causesbreaking of the wiring 678 connecting the via-hole 660D to the solderingbump 675D on which the soldering bump 676D is mounted.

Under such circumstances, it is an object of the present invention toprovide a package board provided with soldering bumps, which can solvethe above conventional problems and never be warped.

It is another object of the present invention to provide a multi-layerwiring board and a multi-layer printed wiring board that are notaffected by noise easily.

It is also another object of the present invention to provide a packageboard that can shorten a transmission path formed between the upperconductor wiring layer and the lower conductor wiring layer.

It is also another object of the present invention to provide a packageboard that will never cause breaking of a wire between soldering bumpand via-hole.

In a package board according to a first aspect of the invention, thesoldering pads on the IC chip side surface of the package board aresmall, so the rate of the metallic portion occupied by those solderingpads is also small. On the other hand, the soldering pads on the motherboard side surface of the package board are large, so the rate of themetallic portion occupied by those soldering pads is also large. This iswhy a dummy pattern is formed between conductor circuit patterns on theIC chip side surface of the package board thereby to increase themetallic portion and adjust the rate of the metallic portion between theIC chip side surface and the mother board side surface of the packageboard so as to protect the package board from warping. The dummy patternmentioned above does not have any functional meaning such as anelectrical connection and a capacitor. It just means a pattern formedmechanically.

In a package board according to a second aspect of the invention, thesoldering pads on the IC chip side surface of the package board aresmall. Thus, the metallic portion occupied by the soldering pads is lessthan that of the mother board side surface of the package board, wherethe soldering pads are large and the metallic portion occupied by thesoldering pads is large. This is why a dummy pattern is formed at theouter periphery of each conductor circuit on the IC chip side surface ofthe package board thereby to increase the metallic portion thereon andadjust the rate of the metallic portion on the package board surfacebetween the IC chip side and the mother board side. This metallic dummypattern is also effective to improve the mechanical strength of theouter periphery of the package board, as well as protect the packageboard from warping.

In a package board according to a third aspect of the invention, a powersupply layer and/or a ground layer is formed as an inner layer conductorcircuit formed under an insulating layer that supports the outermostlayer conductor circuits. Then, a via-hole is connected directly to thesecond conductor circuit and a solder bump is formed in the via-hole. Itis therefore not necessary to provide a wire for connecting the powersupply layer or the ground layer to the soldering bumps. Consequently,the package board is free of any noise to be mixed in wires.

In a package board according to a fourth aspect of the invention, apower supply and/or a ground layer is formed as the second conductorcircuit disposed under the second interlaminar resin insulating layerthat supports the conductor circuits formed in the outermost layer. Avia-hole is connected directly to the second conductor circuit and asoldering bump is formed in the via-hole. It is therefore not necessaryto provide a wire for connecting the power supply layer or the groundlayer to the soldering bumps. Consequently, the package board is free ofany noise to be mixed in wires.

In a package board according to a fifth aspect of the invention, eachland and each pad are formed integrally and connected directly to eachother without using a wire. It is thus possible to shorten thetransmission path provided between upper and lower conductor layers, aswell as to reduce the connecting resistance significantly. In addition,since the land and the pad are connected directly to each other withoutusing a wire, no stress is concentrated at a joint between wiring andland, as well as at a joint between wiring and pad. It is thus possibleto protect the package board from breaking of a wire to be caused by acrack generated by such concentrated stress.

In a package board according to a sixth aspect of the invention, asoldering bump is formed in a via-hole, so that each soldering bump isconnected directly to a via-hole. Therefore, even when the package boardis cracked, it is prevented that breaking of a wire occurs between thesoldering bump and the via-hole. In other words, the conventionalpackage board, where a soldering pad is connected to a via-hole througha wire and a soldering bump is formed on a soldering pad, cannot avoidcrack-caused breaking of a wire connecting via-holes to soldering pads.A soldering bump is thus disconnected from a via-hole due to such acrack generated inside the package board. The package board defined inthis aspect of the invention, however, is completely protected frombreaking of a wire caused by such a crack.

In a package board according to a seventh aspect of the invention, asoldering bump is formed in a via-hole, so that each soldering bump isconnected directly to each via-hole. It is thus possible to preventbreaking of a wire between a soldering bump and a via-hole even when thepackage board is cracked. Such a soldering bump is also formed in aplurality of via-holes respectively in this case. It is possible toutilize a fail-safe, since the soldering bump can be connected toanother via-hole when one of the via-holes is disconnected from thesoldering bump. In addition, since a soldering bump is formed on aplurality of via-holes, a soldering bump can be formed larger to eachvia-hole.

In the present invention, a dummy pattern may be electrically connectedto a power supply layer or a ground layer, or may be the power supplylayer or a ground layer, for reducing noise in signal lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of the package board in a firstembodiment of the present invention.

FIG. 2 is an X1—X1 line cross sectional view of the package board shownin FIG. 1.

FIGS. 3 to FIG. 9 illustrate manufacturing processes of the packageboard in the first embodiment of the present invention.

FIG. 10 is a cross sectional view of the package board in a secondembodiment of the present invention.

FIG. 11A is a top view of the package board in the second embodiment andFIG. 11B is a bottom view of an IC chip.

FIG. 12 is a cross sectional view of the package board shown in FIG. 10when the package board with an IC chip mounted thereon is attached to amother board.

FIG. 13 is a cross sectional view of a multi-layer printed wiring boardin a third embodiment of the present invention.

FIG. 14 is a cross sectional view of a configuration of a variation ofthe multi-layer printed wiring board in the third embodiment of thepresent invention.

FIG. 15 is a cross sectional view of the package board in the fourthembodiment of the present invention.

FIG. 16A is a top view of a core board of the package board in thefourth embodiment of the present invention. On the core board is formedan inner layer copper pattern. FIG. 16B is an expanded partial top viewof FIG. 16A.

FIG. 17 is a cross sectional view of a package board composed as avariation of the package board in the fourth embodiment of the presentinvention.

FIG. 18A is a top view of a conductor circuit formed on a package boardcomposed as a variation of the package board in the fourth embodiment ofthe present invention. FIG. 18B is an expanded partial top view of FIG.18A.

FIG. 19 is a cross sectional view of the package board in a fifthembodiment of the present invention.

FIG. 20 is a cross sectional view of the package board shown in FIG. 19when the package board with an IC chip mounted thereon is attached to amother board.

FIG. 21 is a cross sectional view of a package board composed as avariation of the package board in the fifth embodiment of the presentinvention.

FIG. 22 is an X5—X5 line cross sectional view of the package board shownin FIG. 21.

FIG. 23 is a cross sectional view of a prior art package board.

FIG. 24A is a top view of an inner layer conductor circuit shown in FIG.23, FIG. 24B is a C-line view of FIG. 23, and FIG. 24C is a D-line viewof FIG. 23.

BEST MODE FOR CARRYING OUT THE INVENTION FIRST EMBODIMENT

Hereunder, a configuration of the package board in the first embodimentof the present invention will be described with reference to FIG. 1.FIG. 1 shows a cross sectional view of the package board in the firstembodiment. The package board in this first embodiment is a so-called ICpackage provided with an IC (not illustrated) mounted thereon andattached to a mother board (not illustrated). The package board isprovided with soldering bumps 76U on its top surface and soldering bumps76D on its bottom surface. Each of the soldering bumps 76U is connectedto a soldering bump of the IC and each of the soldering bumps 76D isconnected to a soldering bump of the mother board. Both soldering bumps76U and 76D are used to pass signals between the IC and the motherboard, as well as relay a supply power from the mother board to otherparts.

On both top and bottom surfaces of a core board 30 of the package boardare formed inner layer copper patterns 34U and 34D, which are used asground layers. In the upper layer of the inner layer copper pattern 34Uis formed a conductor circuit 58U, as well as a dummy pattern 58M forforming a signal line with an interlaminar resin insulating layer 50therebetween. In addition, a via-hole 60U is formed through theinterlaminar resin insulating layer 50. In the upper layer of theconductor circuit 58U and the dummy pattern 58M is formed a via-hole160U respectively with an interlaminar resin insulating layer 150therebetween. The via-hole 160U goes through both outermost conductorcircuit 158U and interlaminar resin insulating layer 150. And, asoldering pad 75U is formed both in the conductor circuit 158U and inthe via-hole 160U. The soldering pad 75U is used to support a solderingbump 76U. Each IC chip side soldering pad 75U is formed so as to be 133to 170 μm in diameter.

On the other hand, in the upper layer of the ground layer (inner layercopper pattern) 34D formed on the bottom surface of the core board 30(the upper layer mentioned here means a layer formed on the top surfaceand the lower layer means a layer formed on the bottom surface of theboard 30 respectively) is formed a conductor circuit 58D for forming asignal line with an interlaminar resin insulating layer 50 therebetween.In the upper layer of the conductor circuit 58D is formed a via-hole160D through both an outermost layer conductor circuit 158D and aninterlaminar resin insulating layer 150 with an interlaminar resininsulating layer 150 therebetween. And, a soldering pad 75D is formedboth in the conductor circuit 158D and in the via-hole 160D. Thesoldering pad 75D is used to support a soldering bump 76D. Each motherboard side soldering pad 75D is formed so as to be 600 μm in diameter.

FIG. 2 shows an X1—X1 line cross sectional view of FIG. 1. In otherwords, FIG. 2 shows a cross sectional view of the package board. TheX1—X1 line cross sectional view in FIG. 2 is equal to FIG. 1. As shownin FIG. 2, a dummy pattern 58M is formed between conductor circuits 58Uforming signal lines. A dummy pattern mentioned here means a patternjust formed mechanically; it has no functional meaning such as anelectrical connection, a capacitor, etc.

Just like the prior art package board described above with reference toFIG. 23, according to the package board in the first embodiment of thepresent invention, each soldering pad disposed on the IC chip sidesurface is small (133 to 170 μm in diameter), so the metallic portionoccupied by such soldering pads is also small. On the other hand, sinceeach soldering pad is large (600 μm in diameter) on the mother boardside surface (bottom) of the package board, a larger metallic portion isoccupied by the soldering pads. This is why a dummy pattern 58M isformed between conductor circuits 58U forming a signal line respectivelyon the IC chip side surface of the package board thereby to increase themetallic portion and adjust the rate of the metallic portion on thesurface of the package board between the IC chip side and the motherboard side. It is thus possible to protect the package board fromwarping in the manufacturing processes to be described later, as well asduring a usage of the package board.

Next, how to manufacture the package board shown in FIG. 1 will bedescribed concretely. At first, description will be made for A.Electroless Plating Binding Material, B. Interlaminar Resin InsulatingMaterial, C. Resin Filler, and D. Solder Resist Composition in order.

A. Raw Material Compositions for Manufacturing a Binding Material forElectroless Plating (Upper Layer Binding material)

[Resin Composition (1)]

This resin composition was obtained by mixing and stirring 35 weightparts of a resin solution obtained by dissolving 25% acrylic-modifiedcresol novolac epoxy resin (Nippon Kayaku, molar weight 2500) into DMDGat a concentration of 80 wt %; 3.15 weight parts of photosensitivemonomer (Toagosei, ARONIX M315); 0.5 weight part of an anti-formingagent (SANNOPCO, S-65); and 3.6 weight parts of NMP.

[Resin Composition (2)]

This resin composition was obtained by mixing 12 weight parts ofpolyether-sulfone (PES); 7.2 weight parts of epoxy resin particles(Sanyo Chemical Industries, Polymer Pole) 1.0 μm in average diameter;and 3.09 weight parts of the same epoxy resin particles 0.5 μm inaverage particle diameter; then adding 30 weight parts of NMP to themixture and stirring the mixture using a beads mill.

[Hardener Composition (3)]

This hardener composition was obtained by mixing and stirring 2 weightparts of an imidazole hardener (Shikoku Chemicals, 2E4MZOCN); 2 weightparts of a photo-initiator (Ciba Geigy, Irgacure I-907); 0.2 weight partof a photosensitizer (Nippon Kayaku, DETX-S); and 1.5 weight parts ofNMP.

B. Raw Material Compositions for Manufacturing an Interlaminar ResinInsulating Material (Lower Layer Binding Material)

[Resin Composition (1)]

This resin composition (1) was obtained by mixing and stirring 35 weightparts of a resin solution obtained by dissolving 25% acrylated cresolnovolac epoxy resin (Nippon Kayaku, molar weight 2500) into DMDG at aconcentration of 80 wt %; 4 weight parts of photosensitive monomer(Toagosei, ARONIX M315); 0.5 weight part of an anti-forming agent(SANNOPCO, S-65); and 3.6 weight parts of NMP.

[Resin Composition (2)]

This resin composition (2) was obtained by mixing 12 weight parts ofpolyether-sulfone (PES); 14.49 weight parts of epoxy resin particles(Sanyo Chemical Industries, Polymer Pole) 0.5 μm in average diameter;then adding 30 weight parts of NMP to the mixture and stirring themixture using a beads mill.

[Hardener Composition (3)]

This hardener composition (3) was obtained by mixing and stirring 2weight parts of an imidazole hardener (Shikoku Chemicals, 2E4MZOCN); 2weight parts of a photo-initiator (Ciba Geigy, Irgacure I-907); 0.2weight part of a photosensitizer (Nippon Kayaku, DETX-S); and 1.5 weightparts of NMP.

C. Raw Material Compositions for Manufacturing a Resin Filler

[Resin Composition (1)]

This composition (1) was obtained by mixing and stirring 100 weightparts of bisphenol F type epoxy monomer (Yuka Shell, molecular weight310, YL983U); 170 weight parts of SiO₂ ball-like particles (Admatec, CRS1101-CE, the maximum size of particles should be the thickness (15 μm)of the inner layer copper pattern to be described later) 1.6 μm inaverage diameter, when their surfaces are coated with a silane couplingagent; and 1.5 weight parts of a leveling agent (SANNOPCO, PERENOL S4);then adjusting the viscosity of the mixture to 45,000 to 49,000 cps at23±1° C.

[Hardener Composition (2)]

6.5 weight parts of imidazole hardener (Shikoku Chemicals, 2E4MZ-CN)

D. Solder Resist Composition

This solder resist composition was obtained by mixing 46.67 g ofphotosensitive oligomer (molecular weight 4000) obtained byacrylic-modifying 50% of epoxy groups of 60 percentage by weight ofcresol novolac dissolved into DMDG of 50% epoxy resin (Nippon Kayaku);15.0 g of 80 percentage by weight of bisphenol A type epoxy resin (YukaShell, Epikote 1001) dissolved into methyl ethyl ketone; 1.6 g ofimidazole hardener (Shikoku Chemicals, 2E4MZ-CN); 3 g of multivalentacrylic monomer (Nippon Kayaku, R604) which is photoreceptive monomer;1.5 g of the same multivalent acrylic monomer (KYOEISHA CHEMICAL,DPE6A); 0.71 g of a scattering anti-foaming agent (SANNOPCO, S-65); thenadding 2 g of benzophenone (KANTA CHEMICAL) used as a photoinitiator;and 0.2 g of Michler's ketone (KANTO CHEMICAL) used as a photosensitizerto the mixture and adjusting the viscosity to 2.0 Pa.s at 25° C.

A rotor No. 4 viscosity meter (Tokyo Keiki, DVL-B type) was used tomeasure the viscosity at 60 rpm and a rotor No. 3 B type viscosity meter(Tokyo Keiki, DVL-B type) was used to measure the viscosity at 6 rpm.

Next, description will be made for how to manufacture a package board100 with reference to FIGS. 3 to 9.

E. Manufacturing a Package Board

(1) A copper-clad laminate 30A was obtained at first by laminating 18 μmcopper foil 32 on both surfaces of a board 30 made of glass epoxy resinor BT (bismaleimide triazine) resin of 1 mm in thickness (process A inFIG. 3). After this, the copper-clad laminate 30A was drilled to makeholes, then electroless-plated and etched for patterning thereby to forminner layer copper patterns 34U and 34D on both surfaces of the board 30and make through-holes 36 in the board 30 (process (B) in FIG. 3)).

(2) After forming the inner layer copper patterns 34U and 34D, as wellas through-holes 36, the board 30 was washed in water and dried. Then,the board was treated with oxidation-reduction using NaOH (10 g/l),NaCl02 (40 g/l), and Na3P04 (6 g/l) as oxidation bathing (blackeningbathing) agents and using NaOH (10 g/l) and NaBH4 (6 g/l) as reductionagents thereby to form a rough layer 38 on the surface of each of theinner layer copper patterns 34U and 34D, as well as the through-holes 36(process (C) in FIG. 3)).

(3) The raw material compositions for adjusting the resin filler in Cwere mixed and stirred to obtain a resin filler.

(4) The resin filler 40 obtained in (3) was coated on both surfaces ofthe board 30 within 24 hours after the manufacturing using a rollcoating device thereby to fill a clearance between the conductorcircuits (inner layer copper patterns) 34U, as well as in thethrough-holes 36. The filler was then dried at 70° C. for 20 minutes. Onthe other surface, the resin filler 40 was filled in a clearance betweenthe conductor circuits 34D or in the through-holes 36 and dried at 70°C. for 20 minutes (process (D) in FIG. 3)).

(5) After the treatment (4), one surface of the board 30 was sandedusing a belt sanding machine and a #600 belt sand paper (SankyoRikagaku) to remove the resin filler 40 completely from the surfaces ofboth inner layer copper patterns 34U and 34D, as well as from thesurface of the land 36a of each through-hole 36. After this, the surfaceof the board 30 was buffed to remove scratches made by the belt sanding.Such a series of sanding was also carried out for the other surface ofthe board in the same way (process (E) in FIG. 4)).

After this, the resin filler 40 was hardened by baking at 100° C. forone hour, at 120° C. for three hours, at 150° C. for one hour, and at180° C. for seven hours respectively.

In this way, the surface layer of the resin filler 40 was removed fromthe through-holes 36, etc., and the rough layer of the top surface ofthe inner layer conductor circuits 34U and 34D was removed thereby tosmooth both surfaces of the board 30. It was thus possible to obtain awire board on which the resin filler 40 was in close contact with sidesurfaces of each of the inner layer conductor circuits 34 with a roughlayer 38 therebetween, as well as the resin filler 40 was in closecontact with the inner wall of each through-hole 36 with a rough layer38 therebetween. In other words, this process was effective to align thesurfaces of the resin filler 40 and the inner layer copper pattern 34 onthe same level.

(6) After forming the conductor circuits 34U and 34D, the board 30 wasalkaline-degreased for soft-etching, then the board 30 was treated witha catalyst solvent consisting of palladium chloride and organic acidthereby to add a Pd catalyst. The catalyst was then activated, and theboard 30 was dipped in an electroless plating solvent consisting of3.2×10⁻² mol/l of copper sulfate, 3.9×10⁻³ mol/l of nickel sulfate,5.4×10⁻² mol/l of a complexing agent, 3.3×10⁻¹ mol/l of sodiumhypophosphite, 5.0×10⁻¹ mol/l of boracic acid, 0.1 g/l of a surfaceactive agent (Nissin Chemical Industry, Surfynol 465), and PH=9. Oneminute later, the board 30 was vibrated in both vertical and horizontaldirections once every 4 seconds thereby to form a needle-like alloy,coating layer consisting of Cu—Ni—P and a rough layer 42 on the surfacesof each of the conductor circuits 34, as well as on the surface of theland 36a of each of the through-holes 36 (process (F)) in FIG. 4).

Furthermore, an Sn layer of 0.3 μm in thickness (not illustrated) wasformed on the surface of the rough layer by a Cu-Sn substitutionreaction on the conditions of 0.1 mol/l of boracic stannous fluoride,1.0 mol/l of thiocarbamide, 35° C., and PH=1.2.

(7) The raw material compositions used to adjust the interlaminar resininsulator obtained in B were stirred and mixed thereby to obtain aninterlaminar resin insulator (for lower layers). The viscosity of thelayer was then adjusted to 1.5 Pa.s.

After this, the raw material compositions used to manufacture a bindingmaterial of electroless plating obtained in A were stirred and mixedthereby to obtain a binding solution (for the upper layer) forelectroless plating. The viscosity of the solution was then adjusted to7 Pa.s.

(8) Both surfaces of the board obtained in (6) were coated with aninterlaminar resin insulation material (for lower layers) 44 of 1.5 Pa.sin viscosity using a roll coating device within 24 hours after thesolution was manufactured. Then, the board was left horizontally for 20minutes, then dried (prebaking) at 60° C. for 30 minutes. After this,the board was coated with a sensitive binding solution 46 (for upperlayers) of 7 Pa.s in viscosity obtained in (7) within 24 hours after thesolution was manufactured, then the board was left horizontally for 20minutes. Then, the board was dried (prebaking) at 60° C. for 30 minutesthereby to form a binding material layer 50a of 35 μm in thickness(process (G) in FIG. 4)).

(9) A photo-making film (not illustrated) provided with 85 μmφ printedblack circles was stuck fast to each surface of the board 30 on which abinding layer was formed respectively in (8), then exposed at 500 mJ/cm²using a super high voltage mercury lamp. A DMTG solution was thensprayed on the black circle for developing. Furthermore, the board 30was exposed at 3000 mJ/cm² using a super high voltage mercury lamp, thenheated (post-baking) at 100° C. for one hour, at 120° C. for one hour,and at 150° C. for 3 hours thereby to form an interlaminar resininsulating layer (two-layer structure) of 35 μm in thickness. The layerwas thus provided with 85 μmφ openings (used to form via-holes), whichwere excellent in size accuracy, functioning equally to a photo-maskingfilm (process (H) in FIG. 5)). The tinned layer (not illustrated) waspartially exposed in each of the openings 48 to be used as via-holes.

(10) The board 30 provided with the openings 48 was then dipped inchromic acid for 19 minutes thereby to melt and remove epoxy resin fromthe surface of the interlaminar resin insulation layer 50 and make thesurface rough (process (I) in FIG. 5)). After this, the board 30 wasdipped in a neutralized solution (SHIPLEY), then washed by water.

A palladium catalyst (Atotech) was thus applied to the roughened surface(roughened depth 6 μm) of the board 30 to stick catalytic nuclei on thesurface of the interlaminar resin insulating layer 50, as well as theinner wall surface of each of the via-hole openings 48.

(11) The board was then dipped in an electroless copper plating watersolution consisting of the following compositions thereby to form anelectroless copper plating film 52 of 0.6 μm in thickness on the wholerough surface of the board 30 (process (J) in FIG. 5)).

[Electroless Plating Water Solution]

-   -   EDTA . . . 150 g/l    -   Copper sulfate . . . 20 g/l    -   HCHO . . . 30 ml/l    -   NaOH . . . 40 g/l    -   α,α′-bipyridyl . . . 80 mg/l    -   PEG . . . 0.1 g/l        [Electroless Plating Conditions]    -   30 min. at a solution temperature of 70° C.

(12) A market-sold photosensitive dry film was stuck on the electrolesscopper plating film 52 formed in (11), then a mask was put on the filmfor exposing at 100 mJ/cm² and for developing using 0.8% sodium therebyto form a plating resist 54 of 15 μm in thickness (process (K) in FIG.6)).

(13) After this, the no-resist-formed portion was plated withelectrolytic copper thereby to form an electrolytic copper plated film56 of 15 μm in thickness (process (L) in FIG. 6)).

[Electrolytic Plating Water Solution]

-   -   Sulfuric acid . . . 180 g/l    -   Copper sulfate . . . 80 g/l    -   Additive (Atotech Japan, Cupracid GL) . . . 1 ml/l        [Electrolytic Plating Conditions]    -   Current density . . . 1 A/dm²    -   Time . . . 30 min.    -   Temperature . . . Room temp.

(14) The plating resist 54 was separated and removed with 5%KOH, thenthe electroless plated film 52 under the plating resist was melted andremoved with etching treatment using a mixed solution of sulfuric acidand hydrogen peroxide thereby to form conductor circuits 58U and 58D of18 μm in thickness respectively, as well as via-holes 60U and 60Dconsisting of an electroless copper plated film 52 and an electrolyticcopper plated film 56 respectively (process (M) in FIG. 6)).

(15) The same treatments as those in (6) were carried out to form arough surface 62 consisting of Cu—Ni—P on the surfaces of the conductorcircuits 58U and 58D, as well as the surfaces of the via-holes 60U and60D. Furthermore, Sn displacement was carried out for the rough surface62 (process (N) in FIG. 7)).

(16) The processes (7) to (15) were repeated to form conductor circuitsin a further upper layer. In other words, both surfaces of the board 30were coated with an interlaminar resin insulating material (for lowerlayers) using a roll coating device to form an insulating layer 144. Inaddition, this insulating layer 144 was coated with a photosensitivebinding material (for upper layers) using a roll coating device to forma binding material layer 146 (process (O) in FIG. 7)). After this, aphoto-masking film was stuck fast to both surfaces of the board 30 onwhich the layers 144 and 146 were formed, then exposed and developed toform an interlaminar resin insulating layer 150 provided with openings(via-holes 148). The surface of the interlaminar resin insulating layer150 was then roughened (process (P) in FIG. 7)). After this, anelectroless copper plated film 152 was formed on the roughened surfaceof the board 30 (process (Q) in FIG. 8)). It was followed by forming ofa plating resist 154 on the electroless copper plated film 152, then byforming of an electrolytic copper plated film 156 on theno-resist-coated portion of the film 152 (process (R) in FIG. 8)). Theplating resist 154 was then separated and removed with KOH, and theelectroless plated film 152 under the plating resist 54 was melted andremoved thereby to form conductor circuits 158U and 158D, as well asvia-holes 160U and 160D (process (S) in FIG. 8)). Then, a roughenedlayer 162 was formed on the roughened surface 162 formed on the surfacesof the conductor circuits 158 and the via-holes 160 (process (T). inFIG. 9)). No Sn displacement was carried out for the roughened surface162 at this time.

(17) Both surfaces of the board 30 obtained in (16) were coated with asolder resist composition 70a described in D at a thickness of 45 μm.The board 30 was then dried at 70° C. for 20 minutes, then at 70° C. for30 minutes. After this, a photo-masking film (not illustrated) of 4 mmin thickness on which circles (masking pattern) were drawn was stuckfast to both surfaces of the board 30 respectively, then exposed with anultraviolet beam of 1000 mJ/cm² and developed with DMTG. In addition,the board 30 was baked at 80° C. for 1 hour, at 100° C. for 1 hour, at120° C. for 1 hour, and at 150° C. for 3 hours thereby to form a solderresist layer (20 μm thick) provided with an opening (200 μm diameter) 71at each soldering pad (including the via-hole and its land) (process (U)in FIG. 9)).

(18) After this, the board 30 was dipped in an electroless nickelplating solution of pH=4.5 for 20 minutes to form a nickel plated layer72 of 5 μm in thickness. The electroless nickel plating solutionconsisted of 2.31×10⁻¹ mol/l of nickel chloride, 2.8×10⁻¹ mol/l ofsodium hypophosphite, and 1.85×10⁻¹ of sodium citrate. The board 30 wasthen dipped in an electroless gold plating solution for 7 minutes 20seconds at 80° C. to form a gold plated layer 74 of 0.03 μm in thicknesson the nickel plated layer, so that soldering pads 75U and 75D wereformed on the via-holes 160U and 160D, as well as on the conductorcircuits 158U and 158D (see. FIG. 1). The electroless gold platingsolution consisted of 4.1×10⁻² mol/l of gold potassium cyanide,1.87×10⁻¹ mol/l of ammonium chloride, 1.16×10⁻¹ mol/l of sodium citrate,and 1.7×10⁻¹ mol/l of sodium hypophosphite.

(19) Soldering paste was printed in the openings 71 of the solder resistlayer 70 and reflowed at 200° C. thereby to form soldering bumps(soldering bodies) 76U and 76D. This completed manufacturing of thepackage board 10 (see FIG. 1).

Although the package board was formed with the semi-additive process inthe above embodiment, the configuration of the present invention mayalso apply to a package board to be formed with the full-additiveprocess, of course.

Although a dummy pattern 58M is formed between conductor circuits 58Uformed between the interlaminar resin insulating layer 50 and theinterlaminar resin insulating layer 150 in the first embodiment, such adummy pattern 58M may also be formed between the inner layer copperpatterns 34D formed on the core board 30 or between outermost layerconductor circuits 158U.

As described above, according to the package board in the firstembodiment, a dummy pattern is formed between conductor circuits thatform signal lines on the IC chip side surface of the package boardthereby to increase the metallic portion on the IC chip side surface ofthe package board and adjust the rate of the metallic portion betweenthe IC chip side and the mother board side on the package board. It isthus possible to protect the package board from warping in themanufacturing processes, as well as during operation.

SECOND EMBODIMENT

Hereunder, a configuration of the package board in the second embodimentof the present invention will be described with reference to FIGS. 10 to12. FIG. 10 is a cross sectional view of the package board in the secondembodiment. FIG. 11A is a top view of the package board and FIG. 11B isa bottom view of an IC chip mounted on the package board. FIG. 12illustrates how the IC chip 80 is mounted on the top of the packageboard shown in FIG. 10 as a cross sectional view of the package boardmounted on a mother board 90. The package board is provided withsoldering bumps 76U on its top surface and soldering bumps 76D on thebottom surface as shown in FIG. 12. Those bumps are connected to thebumps 82 of the IC chip 80 and the bumps 92 of the mother board 90respectively. Those bumps are used to pass signals between the IC chip80 and the mother board 90, as well as relay a supply power from themother board to other parts.

As shown in FIG. 10, on both top and bottom surfaces of the core board30 of the package board are formed inner layer copper patterns 34U and34D, which are used as ground layers. In the upper layer of the innerlayer copper pattern 34U is formed a conductor circuit 58U for forming asignal line with an interlaminar resin insulating layer 50 therebetweenand a via-hole 60U through the interlaminar resin insulating layer 50.In the upper layer of the conductor circuit 58U are formed the outermostlayer conductor circuits 158U with an interlaminar resin insulatinglayer 150 therebetween, as well as via-holes 160U through both a dummypattern 159 and an interlaminar resin insulating layer 150. The dummypattern 159 is formed at the outer periphery of each of the conductorcircuits 158U as shown in FIG. 11, that is, along the circumference ofthe package board. On each of the conductor circuits 158U and via-holes160U is formed a soldering pad 75U for supporting a soldering bump 76U.The soldering pads 75U on the IC chip side surface are formed so as tobe 120 to 170 μm in diameter.

On the other hand, in the upper layer of the ground layer (inner layercopper pattern) on the bottom side of the core board 30 are formedconductor circuits 58D for forming signal lines with the interlaminarresin insulating layer 50 therebetween. In the upper layer of theconductor circuits 58D are formed the outermost layer conductor circuits158D with the interlaminar resin insulating layer 150 therebetween, aswell as via-holes 160D through the interlaminar resin insulating layer150. On each of the conductor circuits 158D and the via-holes 160D isformed a soldering pad 75D for supporting a soldering bump 76D. Thesoldering pads 75D on the mother board side surface are formed so as tobe 600 to 700 μm in diameter.

FIG. 11A is a top view of the package board 200, that is, an A-line viewof FIG. 10. FIG. 10 is equal to the X2—X2 line vertical cross sectionalview of FIG. 11A. As shown in FIG. 11A and FIG. 10, at the outerperiphery of each of the conductor circuits 158U for forming signallines on the lower layer of the solder resist 70 is formed a 10 mm-widedummy pattern 159. The dummy pattern mentioned here means a patternformed just mechanically; it has no functional meaning such as anelectric connection, capacitor, etc.

Like the package board manufactured with the prior art described abovewith reference to FIG. 23, according to the package board in the secondembodiment, the IC chip 80 side (top) surface of the package board isprovided with smaller soldering pads 76U (120 to 170 μm in diameter), sothe metallic portion occupied by those soldering pads on the surface ofthe package board is also small. On the other hand, the mother board 90side (bottom) surface of the package board is provided with largersoldering pads 75D (600 to 700 μm in diameter), so the metallic portionoccupied by those soldering pads on the surface of the package board isalso large. This is why the package board in this embodiment forms adummy pattern 159 at the outer periphery of each of the outermost layerconductor circuits 158U on the IC chip side surface of the package boardthereby to increase the metallic portion on the surface and adjust therate of the metallic portion between the IC chip side and the motherboard side on the surface of the package board. The dummy patterns 159are also effective to improve the mechanical strength of thecircumference of the package board, protecting the package board fromwarping in the manufacturing processes, as well as during operation.

FIG. 11A shows a top view (A-line view of FIG. 10) of a completedpackage board and FIG. 11B shows a bottom view of an IC chip. Thepackage board 100, while the IC chip 80 is put thereon, is passedthrough a reflowing oven to fix the IC chip on the package board throughthe soldering bumps 76U as shown in FIG. 12. After this, the packageboard 100 with the IC chip mounted thereon is mounted on a mother board90, then passed in a reflowing oven thereby to fix the package board onthe mother board 90.

How to manufacture the package board in this second embodiment to thefifth embodiment to be described later will be omitted here, since it isthe same as the method described in the first embodiment with referenceto FIGS. 3 to 9.

In the second embodiment described above, a dummy pattern 159 is formedaround each of the outermost layer conductor circuits 158U formed on theinterlaminar resin insulating layer 150. However, the dummy pattern 159may also be formed around each conductor circuit 58U formed betweeninner layer copper patterns 34D or around each of the conductor circuits58U formed between the interlaminar resin insulating layers 50 and 150.

As described above, according to the package board in the secondembodiment, a dummy pattern is formed around each conductor circuit onthe IC chip side surface of the package board thereby to increase themetallic portion on the surface and adjust the rate of the metallicportion between the IC chip side and the mother board side on thesurface of the package board, protecting the package board from warpingin the manufacturing processes, as well as during operation.

THIRD EMBODIMENT

Hereunder, a configuration of the package board in the third embodimentof the present invention will be described with reference to FIG. 13.

The core board 30 of the package board 300 is provided with inner layercopper patterns 34U used as signal lines and formed on its top surface,as well as inner layer copper patterns 34D used as signal lines andformed on its bottom surface respectively. In the upper layer of eachinner layer copper pattern 34U is formed a conductor circuit 58U thatforms a power supply layer with the interlaminar resin insulating layer50 therebetween. In the upper layer of each conductor circuit 58U isformed an outermost layer conductor circuit 158 with the interlaminarresin insulating layer 150 therebetween, as well as a via-hole 160Uthrough the interlaminar resin insulating layer 150. In the via-hole160U is formed a soldering bump 76U. In other words, the package boardis composed in the third embodiment so that a soldering bump 76U isformed on a via-hole 160U connected to a conductor circuit 58U thatforms a power supply layer. The power supply layer can thus be connecteddirectly to an external bump (not illustrated).

On the other hand, a conductor circuit 58D used as a ground layer isformed in the upper layer of a signal line (inner layer copper pattern)34D with the interlaminar resin insulating layer 50 therebetween on thebottom side of the core board 30. In the upper layer of each conductorcircuit 58D is formed an outermost layer conductor circuit 158D with theinterlaminar resin insulating layer therebetween 150, as well as avia-hole 160D through the interlaminar resin insulating layer 150. Asoldering bump 76D is formed on the via-hole 160D. In other words, thepackage board is composed in this embodiment so that a soldering bump76D is formed on a via-hole 160D connected to a conductor circuit 58Dcomposing a ground layer. The ground layer can thus be connecteddirectly to an external bump (not illustrated).

According to the package board configuration in this embodiment, theconductor circuits 58U and 58D disposed under the interlaminar resininsulating layer 150 supporting the conductor circuits 158U and 158D inthe outermost layer are used as a power supply layer and a ground layer.And, via-holes 160U and 160D are connected directly to the conductorcircuits 58U and 58D, and soldering bumps 76U and 76D are formed in thevia-holes respectively. Consequently, it is not necessary to connect anypower supply layer or ground layer directly to soldering bumps. Thepackage board is thus protected from noise mixed in wires. It is thuspossible to reduce the influence of noise expected while passing signalsbetween the IC and the mother board, as well as while relaying a supplypower from the mother board to other parts. In addition, since there areless wires, the multi-layer printed wiring board (package board) can bepacked more densely. According to the multi-layer printed wiring boardin this embodiment, a conductor circuit 58U is used as a power supplylayer and a conductor circuit 58D is used as a ground layer. Theconductor circuit 58U or 58D, however, may be formed in the same layertogether with other conductor circuits functioning as a power supplylayer and a ground layer respectively.

Next, a description will be made for a multi-layer printed wiring boardcomposed as a variation of the third embodiment with reference to FIG.14.

FIG. 14 is a cross sectional view of a configuration of the multi-layerprinted wiring board in the second embodiment of the present invention.On both top and bottom surfaces of the core board 230 are formed innerlayer copper patterns 234U and 234D used as ground layers. In otherwords, capacitors are formed with the ground layers (inner layer copperpatterns) 234U and 234D that face each other with the core boardtherebetween.

Furthermore, on the upper layer of the inner layer copper pattern 234Uare formed a conductor circuits 258U that form signal lines with theinterlaminar resin insulating layer 250 therebetween. In the upper layerof the conductor circuits 258U are formed via-holes 360U through theinterlaminar resin insulating layer 350. And, a soldering bump 376U isformed on each of those via-holes 360U.

On the other hand, in the upper layer of the ground layer (inner layercopper pattern) 234D formed on the bottom surface of the board 230 isformed a conductor circuit 258D that forms a signal line with theinterlaminar resin insulating layer 250 therebetween. In the upper layerof the conductor circuit 258D is formed a conductor circuit 388D used asa power supply layer with the interlaminar resin insulating layer 350therebetween. In the upper layer of the conductor circuit 388D is formeda via-hole 380D through the interlaminar resin insulating layer 390.And, a soldering bump 376D is formed in the via-hole 380D. In otherwords, a soldering bump 376D is formed in a via-hole 380D connected to aconductor circuit 388D used as a power supply layer. The power supplylayer can thus be connected directly to an external bump (notillustrated).

In the third embodiment, a via-hole 380D is connected directly to theconductor circuit 388D used as a power supply layer and a soldering bump376D is formed in a via-hole. Consequently, it is not necessary toprovide a wire for connecting the power supply layer to soldering bumps.It is thus possible to make the package board free of noise mixed inwires.

As described above, according to the package board in the thirdembodiment, an inner layer conductor circuit formed in the lower layerof the insulating layer supporting the conductor circuits formed in theoutermost layer is used as a power supply layer and/or a ground layer,and a via-hole is connected directly to a second conductor circuit and asoldering bump is formed in each of those via-holes. The package boardcan therefore eliminate a wire for connecting the power supply layer orthe ground layer to soldering bumps. Consequently, it is possible tomake the package board free of noise mixed in wires. Furthermore, thewiring-eliminated space can be used to pack the multi-layer printedwiring board in a higher density.

Furthermore, according to the package board in the third embodiment, asecond conductor circuit formed under the second interlaminar resininsulating layer supporting the outermost layer conductor circuits isused as a power supply layer or a ground layer, and a via-hole isconnected directly to the second conductor circuit and a soldering bumpis formed on the via-hole. The package board can thus eliminate a wirefor connecting the power supply layer or the ground layer to solderingbumps. Consequently, it is possible to make the package board free ofnoise mixed in wires. Furthermore, the wiring-eliminated space can beused to pack the multi-layer printed wiring board more densely.

FOURTH EMBODIMENT

Hereunder, a configuration of the package board in the fourth embodimentof the present invention will be described with reference to FIG. 15. Onboth top and bottom surfaces of the core board 30 of the package board400 are formed inner layer copper patterns 34U and 34D used as a groundlayer respectively. In the upper layer of the inner layer copper pattern34U are formed a conductor circuit 58U that forms a signal line with aninterlaminar resin insulating layer 50 therebetween, as well as avia-hole 60U through the interlaminar resin insulating layer 50. In theupper layer of the conductor circuit 58U is formed an outermost layerconductor circuit 158U with an interlaminar resin insulating layer 150therebetween, as well as a via-hole 160U through the interlaminar resininsulating layer 150. And, a soldering pad 75U for supporting asoldering bump 76U is formed on the conductor circuit 158U and thevia-hole 160U respectively. Each of the soldering pads 75U on the ICchip side surface of the package board is formed so as to be 133 to 170μm in diameter.

On the other hand, in the upper layer of the inner layer copper pattern34D formed on the bottom surface of the core board 30 is formed aconductor circuit 58D that forms a signal line with the interlaminarresin insulating layer 50 therebetween. In the upper layer of theconductor circuit 58D is formed an outermost layer conductor circuit158D with the interlaminar resin insulating layer 150 therebetween, aswell as a via-hole 160D through the interlaminar resin insulating layer150. And, a soldering pad 75D for supporting a soldering bump 76D isformed on the conductor circuit 158D and the via-hole 160D respectively.Each of those soldering pads 75D on this mother board side surface ofthe package board is formed so as to be 600 μm in diameter. In addition,a ground (electrode) layer is formed on each of the inner layer copperpatterns 34U and 34D that face each other with the core board 30therebetween, so that a capacitor is formed with those inner layercopper patterns 34U and 34D.

FIG. 16A is a top view of an inner layer copper pattern 34U formed onthe top surface of the core board 30. On this inner layer copper pattern34U are formed a ground layer 34G and land-pads 41 used to connect theupper layer to the lower layer respectively. FIG. 16B shows an expandedland-pad 41 formed in the B area in FIG. 16A. The X3—X3 line crosssectional view in FIG. 16B is equal to the X3—X3 line cross sectionalview in FIG. 15.

As shown in FIG. 16B, each land-pad 41 is a combination of the land 41aof a through-hole 36 shown in FIG. 15 and a pad 41b connected to avia-hole 60U that goes through the upper interlaminar resin insulatinglayer 50. Around the lad pad 41 is disposed an insulating buffer 43 ofabout 200 μm in width.

According to the package board in this embodiment, a land 41a is unitedwith a pad 41b as shown in FIG. 16B, so that the land 41a is connecteddirectly to the pad 41b without using a wire. It is thus possible toshorten the transmission path between the lower layer (the conductorcircuit 58D) and the upper conductor wiring 58U in the upper layer (theinterlaminar resin insulating layer 50) thereby to speed up the signaltransmission, as well as reduce the connection resistance. In addition,since the land 41a is connected directly to the pad 41b without using awire, no stress is concentrated between a wire and a land or between awire and a pad. The package board is thus protected completely frombreaking of a wire caused by a crack generated by concentrated stress atsuch a place, although the package board manufactured with the prior arttechnology described above with reference to FIG. 24A has confrontedwith such a problem. And, although a description was made for only theinner layer copper pattern 34U formed on the top surface of the coreboard 30, the inner layer copper pattern 34D on the bottom surface ofthe core board 30 is also composed in the same way.

Next, a description will be made for a package board composed as avariation of the fourth embodiment of the present invention withreference to FIGS. 17 and 18. According to the fourth embodimentdescribed above with reference to FIG. 15, the ground layer (electrodelayer) 34G and the land-pad 41 are formed on the inner layer copperpatterns 34U and 34D formed on both top and bottom surfaces of the coreboard 30. On the contrary, in the second embodiment, the power supplylayer (electrode layer) 58G and the land-pad 61 are formed on theconductor circuits 58U and 58D formed in the upper layer of theinterlaminar resin insulating layer 50 as shown in FIG. 16A.

FIG. 17 is a cross sectional view of the package board composed as avariation of the fourth embodiment. FIG. 18A is a top view of theconductor circuit 58U formed on the top surface of the interlaminarresin insulating layer 50. On this conductor circuit 58U are formed apower supply layer 58G, as well as land-pads 61 used to connect theupper layer to the lower layer respectively. FIG. 18B shows an expandedland-pad 61 in the B area shown in FIG. 18A. The X4—X4 line crosssectional view shown in FIG. 18B is equal to the X4—X4 line crosssectional view shown in FIG. 17.

As shown in FIG. 17, each of those land-pads 61 is a combination of theland 61a of a via-hole 60U connected to an inner layer copper pattern34U and a pad 61b connected to a via-hole 160U going through the upperinterlaminar resin insulating layer 150. Around each of those land pad61 is disposed an insulating buffer 63 of about 200 μm in width as shownin FIG. 18B.

Also in the case of this package board composed as a variation of thefourth embodiment, a land 61a is united with a pad 61b, so that the land61ais connected directly to the pad 61b without using a wire. This makesit possible to shorten the transmission between the lower layer (aninner layer copper pattern 34U on the top surface of the core board 30)and an upper first conductor wire 158U formed on the top of the upperlayer (the interlaminar resin insulating layer 150), as well as to speedup the signal transmission and reduce the connection resistance. Inaddition, since the land 61a is connected directly to the pad 61bwithout using a wire, no stress is concentrated between a wire and aland or between a wire and a pad. The package board is thus protectedcompletely from breaking of a wire caused by a crack generated byconcentrated stress at such a place, although the package boardmanufactured with the prior art technology described above withreference to FIG. 24A has confronted with such a problem.

Although each circularly-formed land is united with a pad in the aboveembodiment, the land may be formed as an ellipse, a polygon, etc. andunited with a pad in this invention.

According to the fourth embodiment described above, each land isconnected directly to a pad without using a wire. It is thus possible toshorten the transmission between the lower layer and each conductorwiring (conductor layer) formed in the upper layer, as well as to speedup the signal transmission and reduce the connection resistance. Inaddition, since each land is connected directly to a pad without using awire, no stress is concentrated at a junction between wiring and land,as well as at a junction between wiring and pad. The package board canthus be protected completely from breaking of a wire caused by a crackgenerated by concentrated stress at such a place.

FIFTH EMBODIMENT

Hereunder, a description will be made for a configuration of the packageboard in the fifth embodiment of the present invention with reference toFIGS. 19 and 20. FIG. 19 is a cross sectional view of the package board500 in the fifth embodiment. FIG. 20 shows how the package board 500provided with an IC chip 80 mounted on its top surface thereof ismounted on a mother board 90 thereby to compose a so-called integratedcircuit package.

On both top and bottom surfaces of the core board 30 of the packageboard 500 are formed inner layer copper patterns 34U and 34D used asground layers. In the upper layer of the inner layer copper pattern 34Uis formed a conductor circuit 58U forming a signal line with aninterlaminar resin insulating layer 50 therebetween, as well as avia-hole 60U through the interlaminar resin insulating layer 50. In theupper layer of the conductor circuit 58U is formed an outermost layerconductor circuit 158U with an interlaminar resin insulating layer 150,as well as a via-hole 160U through the interlaminar resin insulatinglayer 150. And, a soldering pad 75U for supporting a soldering bump 76Uis formed on the conductor circuit 158U and the via-hole 160Urespectively. Each of the soldering pads 75U on the IC chip side surfaceof the package board is formed so as to be 133 to 170 μm in diameter.

On the other hand, in the upper layer of the ground layer (inner layercopper pattern) on the bottom side of the core board 30 is formed aconductor circuit 58D forming a signal line with an interlaminar resininsulating layer 50 therebetween. In the upper layer of the conductorcircuit 58D is formed an outermost layer conductor circuit 158D with aninterlaminar resin insulating layer 150 therebetween, as well as avia-hole 160D through the interlaminar resin insulating layer 150. And,a soldering pad 75D for supporting a soldering bump 76D is formed in thevia-hole 160D. Each of the soldering pads 75D on the mother board sidesurface is formed so as to be 600 μm in diameter.

According to this package board in the fifth embodiment, a solderingbump 76D is formed on each via-hole 160D on the mother board sidesurface 60, so that the soldering bump is connected directly to thevia-hole. Consequently, the package board is completely protected frombreaking of a wire, otherwise to occur between the soldering bump 76Dand the via-hole 160D if the package board is cracked. In other words,according to the package board 600 manufactured with the prior arttechnology described above with reference to FIG. 23B, each solderingpad 375D is connected to a via-hole 360 through a wire 378 and asoldering bump 376D is disposed on a soldering pad 375D. If a crack L2is generated in the package board 600, therefore, the crack L2 breaksthe wire 378 connecting the via-hole 376D to the soldering pad 376D. Thesoldering bump 376D can therefore be disconnected from the via-hole360D. On the contrary, according to the package board in the fifthembodiment, no breaking of a wire occurs between the soldering bump 376Dand the via-hole 160D even when a crack is generated in the packageboard.

Next, a description will be made for how the IC chip 80 is mounted onthe package board 500 in the fifth embodiment of the present inventionshown in FIG. 19. As shown in FIG. 20, the IC chip 80 is mounted on thepackage board 500 so that the soldering pads 82 of the IC chip 80 arealigned to the soldering bumps 76U of the package board 500. Then, thepackage board 500 with the IC chip 80 mounted thereon is passed througha heating oven thereby to weld the soldering pads 76U to the solderingpads 82. The IC chip 80 is thus connected to the package board 500.

The package board 500 is then washed to remove the soldering flux seepedout when the soldering bumps 76U are welded to and set up at thesoldering pads 82 in the heating process. In this embodiment, an organicsolution such as chlorothen is flown between the IC chip 80 and thepackage board 500 to remove the soldering flux. Resin is then filledbetween the IC chip 80 and the package board 500 to seal the portion.Although not illustrated, the whole IC chip 80 is molded with resin atthis time thereby to finish the mounting of the IC chip 80 on thepackage board 500.

After this, the soldering pads 92 of the mother board 90 are aligned tothe soldering bumps 76D to mount the package board 500 on a mother board90. Then, the package board is passed through a heating oven to fuse thesoldering pads 76D to the soldering pads 92. The package board 500 isthen connected to the mother board 90. After this, resin 94 is filled ina clearance between the package board 500 and the mother board 90 asshown in FIG. 20 to seal the clearance. This completes the mounting ofthe package:board 500 on the mother board 90.

Next, a description will be made for a package board 501 composed as avariation of the fifth embodiment of the present invention withreference to FIGS. 20 and 21.

According to the package board 500 in the fifth embodiment describedabove with reference to FIG. 19, a soldering bump 76D is formed on avia-hole 160D. Meanwhile, according to the package board 501 in thefifth embodiment, a soldering bump 276 is formed on a plurality of(three) via-holes 260 as shown in FIG. 21. In other words, threevia-holes 260 are formed closely to each other as shown in FIG. 22,which is equal to the X5—X5 line cross sectional view shown in FIG. 21(the X6—X6 line in FIG. 22 is equal to the X5—X5 line in FIG. 21). Then,a nickel plated layer 72 and a gold plated layer 74 are formedrespectively on a common land 260a of the three via-holes 260 thereby toform one large land 275. And, a large soldering bump 276 is formed onthe large land 275.

In the case of this package board 501 composed as a variation of thefifth embodiment, a soldering bump 276 is formed on a plurality ofvia-holes 260, so that the soldering bump 276 is connected directly tothe via-holes 260. Consequently, it is prevented that the soldering bump276 is disconnected from the via-holes 260, for example, even when thepackage board 501 is cracked. In addition, since a soldering bump 276 isformed on a plurality of (three) via-holes 260, the package board 501can have a phase safe function. Because, when one of those via-holes 260is disconnected from the inner layer conductor circuit 58D, anothervia-hole 260 can keep the connection with the soldering bump 27 and theinner layer conductor circuit 58D.

Furthermore, as described above, each soldering pad 75U on the IC chip80 side surface is formed so as to be 133 to 170 μm in diameter and eachsoldering pad 75D on the mother board side surface is formed so as to be600 μm in diameter. Thus, there is generated a difference in solderingpad size 4 to 5 times between the IC chip side and-the mother boardside. It is thus difficult to form a large soldering pad 75D on avia-hole like those formed on the mother board side surface. In the caseof this package board 501 composed as a variation of the fifthembodiment, therefore, a soldering bump 276 is formed on a plurality of(three) via-holes 260, 260, and 260 thereby to form such a largesoldering bump. Although one soldering bump is formed on three via-holesin this variation described above, it is also possible to form onesoldering bump on two via-holes or on four or more via-holes.

According to the package board in the fifth embodiment as describedabove, a soldering bump is formed on a via-hole, so that the solderingbump is connected directly to the via-hole. This can prevent breaking ofa wire even when the package board is cracked between the soldering bumpand the via-hole. In addition, since a soldering bump is formed on aplurality of via-holes, the package board can have a phase safefunction. Because, when one of the via-holes is disconnected from thesoldering bump inside the package board, another via-hole can keep theconnection with the soldering bump. And, since a soldering bump isformed on a plurality of via-holes, the soldering bump can be formedlarger with respect to the via-hole.

Although the package board is connected directly to the mother board inthe embodiment described above, the present invention also allows thepackage board to be connected to the mother board via a sub-board, etc.

1. A package board comprising: a core board, the board board having anIC chip side surface and an other surface opposed to the IC chip sidesurface; a first plurality of conductor circuits formed on the IC chipside surface and a second plurality of conductor circuits formed on theother surface, the first plurality of conductor circuits beingconstructed and adapted configured to be electrically connected to an ICchip; a first interlaminar resin insulating layer disposed between theIC chip side surface and the first plurality of conductor circuits; asecond interlaminar resin insulating layer disposed between the othersurface and the second plurality of conductor circuits; a firstplurality of soldering pads formed on the IC chip side surface; a secondplurality of soldering pads formed on the other surface, the solderingpads of the second plurality being larger than the soldering pads of thefirst plurality; and a dummy pattern constructed and adapted to improvethe mechanical strength of the package board, the dummy pattern beingcomprising a metal and formed at an outer periphery of the firstplurality of conductor circuits such that a rate of metallic portions onthe IC chip side surface and the other surface is adjusted to improvethe mechanical strength of the package board.
 2. A package board,comprising: a core board, the core board having an IC chip side surfaceand an other surface opposed to the IC chip side surface; one or morelayers of conductor circuits formed on the IC chip side surface and oneor more layers of conductor circuits formed on the other surface, theone or more layers of conductor circuits formed on the IC chip sidesurface being constructed and adapted configured to be electricallyconnected to an IC chip; a first interlaminar resin insulating layerdisposed between the core board and the one or more layers of conductorcircuits formed on the IC chip side surface; a second interlaminar resininsulating layer disposed between the core board and the one or morelayers of conductor circuits formed on the other surface; additionalinterlaminar insulating layers disposed between ones of the one or morelayers of conductor circuits formed on the IC chip side surface and theother surface; a first plurality of soldering pads formed on a top oneof the one or more layers of conductor circuits on the IC chip sidesurface; a second plurality of soldering pads formed on a top one of theone or more layers of conductor circuits on the other surface, thesoldering pads of the second plurality being larger than the solderingpads of the first plurality; and a dummy pattern constructed and adaptedto improve the mechanical strength of the package board, the dummypattern being comprising a metal and formed at an outer periphery of atleast one of the one or more layers of conductor circuits on the IC chipside surface such that a rate of metallic portions on the IC chip sidesurface and the other surface is adjusted to improve the mechanicalstrength of the package board.
 3. The package board of claim 1, whereinthe dummy pattern is formed at the outer periphery of each of the one ormore layers of conductor circuits on the IC chip side surface.
 4. Apackage board, comprising: a core board, the core board having an ICchip side surface and an other surface opposed to the IC chip sidesurface; one or more layers of conductor circuits formed on the IC chipside surface and one or more layers of conductor circuits formed on theother surface, the one or more layers of conductor circuits formed onthe IC chip side surface being constructed and adapted configured to beelectrically connected to an IC chip; a first interlaminar resininsulating layer disposed between the core board and the one or morelayers of conductor circuits formed on the IC chip side surface; asecond interlaminar resin insulating layer disposed between the coreboard and the one or more layers of conductor circuits formed on theother surface; additional interlaminar insulating layers disposedbetween one of the one or more layers of conductor circuits formed onthe IC chip side surface and the other surface; a first plurality ofsoldering pads formed on a top one of the one or more layers ofconductor circuits on the IC chip side surface; a second plurality ofsoldering pads formed on a top one of the one or more layers ofconductor circuits on the other surface, the soldering pads of thesecond plurality being larger than the soldering pads of the firstplurality; and a dummy pattern constructed and adapted to improve themechanical strength of the package board, the dummy pattern beingcomprising a metal and formed at an outer periphery of the core board onthe IC chip side surface such that a rate of metallic portions on the ICchip side surface and the other surface is adjusted to improve themechanical strength of the package board.
 5. A package board accordingto claim 4, wherein the metal comprising the dummy pattern and a metalcomprising the one or more layers of conductor circuits on the IC chipside surface are a same metal.
 6. A package board according to claim 2,wherein the metal comprising the dummy pattern and a metal comprisingthe first plurality of conductor circuits are a same metal.
 7. A packageboard according to claim 3, wherein the metal comprising the dummypattern and a metal comprising the first plurality of conductor circuitsare a same metal.
 8. A package board according to claim 1, wherein themetal comprising the dummy pattern and a metal comprising the firstplurality of conductor circuits are a same metal.
 9. A package boardcomprising: a core board; and a plurality of conductor circuits formedwith an interlaminar resin insulating layer therebetween on each surfaceof the core board, wherein a plurality of soldering pads are formed onan IC chip mounted side surface of said core board and on an other sidesurface of said core board to be connected to another board, so thatsaid soldering pads on the other side surface are larger than saidsoldering pads on said IC chip side surface of said package board, andsaid IC chip mounted side surface has a power supply pattern or a grandpattern comprising a metal and formed between signal line conductorcircuit patterns formed on an IC chip mounted side of said core boardsuch that a rate of metallic portions on the IC chip side surface andthe other surface is adjusted to improve the mechanical strength of thepackage board.
 10. A package board according to claim 9, wherein themetal comprising the dummy pattern and a metal comprising the pluralityof conductor circuits are a same metal.
 11. A package board comprising:a core board; and a plurality of conductor circuits formed with aninterlaminar resin insulating layer therebetween on each surface of thecore board, wherein a plurality of soldering pads are formed on an ICchip mounted side surface of said core board and on an other sidesurface of said core board to be connected to another board, so thatsaid soldering pads on the other side surface are larger than saidsoldering pads on said IC chip side surface of said package board, andsaid IC chip mounted side surface has a power supply pattern or a grandpattern comprising a metal and formed between signal line conductorcircuit patterns of an outmost layer formed on an IC chip mounted sideof said core board such that a rate of metallic portions on the IC chipside surface and the other surface is adjusted to improve the mechanicalstrength of the package board.
 12. A package board according to claim11, wherein the metal comprising the dummy pattern and a metalcomprising the plurality of conductor circuits are a same metal.
 13. Apackage board comprising: a core board; and a plurality of conductorcircuits formed with an interlaminar resin insulating layer therebetweenon each surface of the core board, wherein a plurality of soldering padsare formed on an IC chip mounted side surface of said core board and onan other side surface of said core board to be connected to anotherboard, so that said soldering pads on the other side surface are largerthan said soldering pads on said IC chip side surface of said packageboard, and said IC chip mounted side surface has a power supply patternor a grand pattern comprising a metal and formed between signal lineconductor circuit patterns formed on an IC chip mounted side of saidcore board such that a rate of metallic portions on the IC chip sidesurface and the other surface is adjusted to improve the mechanicalstrength of the package board.
 14. A package board according to claim13, wherein the metal comprising the dummy pattern and a metalcomprising the plurality of conductor circuits are a same metal.
 15. Apackage board comprising: a core board; and a plurality of conductorcircuits formed with an interlaminar resin insulating layer therebetweenon each surface of the core board, wherein a plurality of soldering padsare formed on an IC chip mounted side surface of said core board and onan other side surface of said core board to be connected to anotherboard, so that said soldering pads on the other side surface are largerthan said soldering pads on said IC chip side surface of said packageboard, and said IC chip mounted side surface has a power layer or agrand layer comprising a metal and formed between signal line conductorcircuit patterns formed on an IC chip mounted side of said core boardsuch that a rate of metallic portions on the IC chip side surface andthe other surface is adjusted to improve the mechanical strength of thepackage board.
 16. A package board according to claim 15, wherein themetal comprising the dummy pattern and a metal comprising the pluralityof conductor circuits are a same metal.
 17. A package board comprising:a core board; and a plurality of conductor circuits formed with aninterlaminar resin insulating layer therebetween on each surface of thecore board, wherein a plurality of soldering pads are formed on an ICchip mounted side surface of said core board and on an other sidesurface of said core board to be connected to another board, so thatsaid soldering pads on the other side surface are larger than saidsoldering pads on said IC chip side surface of said package board, andsaid IC chip mounted side surface has a power layer or a grand layercomprising a metal and formed between signal line conductor circuitpatterns of an outmost layer formed on an IC chip mounted side of saidcore board such that a rate of metallic portions on the IC chip sidesurface and the other surface is adjusted to improve the mechanicalstrength of the package board.
 18. A package board according to claim17, wherein the metal comprising the dummy pattern and a metalcomprising the plurality of conductor circuits are a same metal.
 19. Apackage board comprising: a core board; and a plurality of conductorcircuits formed with an interlaminar resin insulating layer therebetweenon each surface of the core board, wherein a plurality of soldering padsare formed on an IC chip mounted side surface of said core board and onan other side surface of said core board to be connected to anotherboard, so that said soldering pads on the other side surface are largerthan said soldering pads on said IC chip side surface of said packageboard, and said IC chip mounted side surface has a power layer or agrand layer comprising a metal and formed between signal line conductorcircuit patterns formed on an IC chip mounted side of said core boardsuch that a rate of metallic portions on the IC chip side surface andthe other surface is adjusted to improve the mechanical strength of thepackage board.
 20. A package board according to claim 19, wherein themetal comprising the dummy pattern and a metal comprising the pluralityof conductor circuits are a same metal.